Scaling and variability in ultra thin body silicon on insulator (UTB SOI) MOSFETs

The main objective of this thesis is to perform a comprehensive simulation study of the statistical variability in well scaled fully depleted ultra thin body silicon on insulator (FD-UTB SOI) at nanometer regime. It describes the design procedure for template FDUTB SOI transistor scaling and the impacts of statistical variability and reliability the scaled template transistor. The starting point of this study is a systematic simulation analysis based on a welldesigned 32nm thin body SOI template transistor provided by the FP7 project PULLNANO. The 32nm template transistor is consistent with the International Technology Roadmap for Semiconductor (ITRS) 2009 specifications. The wellestablished 3D ‘atomistic’ simulator GARAND has been employed in the designing of the scaled transistors and to carry out the statistical variability simulations. Following the foundation work in characterizing and optimizing the template 32 nm gate length transistor, the scaling proceeds down to 22 nm, 16 nm and 11 nm gate lengths using typically 0.7 scaling factor in respect of the horizontal and vertical transistor dimensions. The device design process is targeted for low power applications with a careful consideration of the impacts of the design parameters choice including buried oxide thickness (TBOX), source/drain doping abruptness (σ) and spacer length (Lspa). In order to determine the values of TBOX, σ, and Lspa, it is important to analyze simulation results, carefully assessing the impact on manufacturability and to consider the corresponding trade-off between short channel effects and on-current performance. Considering the above factors, TBOX = 10nm, σ = 2nm/dec and Lspa = 7nm have been adopted as optimum values respectively. iv The statistical variability of the transistor characteristics due to intrinsic parameter fluctuation (IPF) in well-scaled FD-UTB SOI devices is systematically studied for the first time. The impact of random dopant fluctuation (RDF), line edge roughness (LER) and metal gate granularity (MGG) on threshold voltage (Vth), on-current (Ion) and drain induced barrier lowering (DIBL) are analysed. Each principal sources of variability is treated individually and in combination with other variability sources in the simulation of large ensembles of microscopically different devices. The introduction of highk/ metal gate stack has improved the electrostatic integrity and enhanced the overall device performance. However, in the case of fully depleted channel transistors, MGG has become a dominant variability factor for all critical electrical parameters at gate first technology. For instance, σVth due to MGG increased to 41.9 mV at 11nm gate length compared to 26.0 mV at 22nm gate length. Similar trend has also been observed in σIon, increasing from 0.065 up to 0.174 mA/μm when the gate length is reduced from 22 nm down to 11 nm. Both RDF and LER have significant role in the intrinsic parameter fluctuations and therefore, none of these sources should be overlooked in the simulations. Finally, the impact of different variability sources in combination with positive bias temperature instability (PBTI) degradation on Vth, Ion and DIBL of the scaled nMOSFETs is investigated. Our study indicates that BTI induced charge trapping is a crucial reliability problem for the FD-UTB SOI transistors operation. Its impact not only introduces a significant degradation of transistor performance, but also accelerates the statistical variability. For example, the effect of a late degradation stage (at trap density of 1e12/cm2) in the presence of RDF, LER and MGG results in σVth increase to 36.9 mV, 45.0 mV and 58.3 mV for 22 nm, 16 nm and 11 nm respectively from the original 29.0 mV, 37.9 mV and 50.4 mV values in the fresh transistors

Wireless temperature sensor network

Sensor networks are being widely deployed for measurement, detection and surveillance applications. Today, humidity becomes very important in many aspects especially in manufacturing industry. Therefore, the use of tools or systems that can monitor the humidity level is very significant. Sensor networks can be used to identify larger trends in temperature which could be used to report energy usage, HVAC problems, computer failures based on high temperatures and fire evacuation route reporting. This project presents a design of Wireless Temperature Sensor Network that capable to monitor the humidity level. This Wireless Temperature Sensor Network comprises of two parts; temperature detection and monitoring. The detection section will sense the temperature and transmit the signal to the monitoring section. All the sensors are connected mote to mote to ensure that each mote can communicate and exchange the data with each other. The collection of temperature data would be obtained by a sensor network. The data was collected using a temperature sensor network connected to a stand-alone computer. This approach can makes the monitoring process becomes more efficient and cost effective. The data (temperature level) will be display by using GUI. In the case of mote to mote system, the GUI capable to display the overall level of temperature

Design And Characterization Of 20nm SOI MOSFET Doping Abruptness Dependent

SOI MOSFET has currently become a trend for low power devices such as palmtops, cell phone, and other devices because it has a lot of advantage in terms of speed, density, and performance gain. Various efforts have been done to continue the progress in shrinking dimensions and higher-frequency performance will be driven by the market application. Reducing the size of SOI MOSFET will reduce the power, body effect, and parasitic capacitance, and increase the density and so on. This project focused mainly on the source/drain doping abruptness of SOI MOSFET. The doping abruptness was varied to find the best doping profile since the device was shrinking. In order to vary the source/drain doping abruptness, there were several problems to be encountered, which were increase in resistance, increase in threshold voltage, small sub-threshold slope, and others. The purpose of this project was to design the SOI MOSFET with an ideal doping profile and to investigate the impact on threshold voltage, current, and sub-threshold slope due to the variation of source/drain doping abruptness of SOI MOSFET. This project was designed using Silvaco Athena and Silvaco Atlas. Silvaco Athena was used to simulate the device structure and Silvaco Atlas was used to obtain the device characteristics of SOI MOSFET. This whole project was implemented on an SOI MOSFET doping abruptness dependent with a gate length of 21 nm

Back-gate bias dependence of the statistical variability of FDSOI MOSFETs with thin BOX

The impact of back-gate bias on the statistical variability (SV) of FDSOI MOSFETs with thin buried oxide (BOX) is studied via 3-D 'atomistic' drift-diffusion simulation. The impact of the principal sources of SV, i.e., random dopant fluctuations, line edge roughness, and metal gate granularity, on threshold voltage, drain-induced barrier lowering, and drive current is studied in detail. It is shown that reverse back-bias is beneficial in terms of reducing the dispersion of the off-current and the corresponding standby leakage power, whereas forward back-bias reduces the on-current variability. The correlation coefficients between relevant figures of merit and their trends against back-bias are also studied in detail, providing guidelines for the development of statistical compact models of thin-BOX FDSOI MOSFETs for low-standby-power circuit applications. © 1963-2012 IEEE.published_or_final_versio

Impact of Different Dose, Energy and Tilt Angle in Source/Drain Implantation for Vertical Double Gate PMOS Device

In this paper, an investigation on the impact of different dose, energy and tilt angle of Source/Drain (S/D) implantation towards threshold voltage (VTH) value in vertical double-gate PMOS device was conducted by using L8 2k-factorial design. The level of significance for each process parameters on VTH was determined by using analysis of variance (ANOVA). The virtual fabrication and electrical characterization of the device were performed by using a process simulator (ATHENA) and a device simulator (ATLAS) respectively. This procedure was followed by 2k-factorial design to aid in optimizing the process parameter variations towards VTH value. Based on the final results, the most dominant factor that affects VTH value was found to be S/D implant energy. Meanwhile, the nominal possible VTH value after the optimization analysis was observed to be – 0.4509V. The percentage difference is only 0.87% higher than ITRS 2013 prediction for low power (LP) requirement in the year 2020

Design of Shallow Source/Drain Extension (SDE) Profiles in Improving Short -Channel Effect (SCE) in Nanoscale Devices

This paper purposed the design of shallow source/drain extension (SDE) in improving short channel effect (SCE) in nanoscale devices. In order to increase the mobility and the speed of the electronic devices, semiconductor technology researchers face the limitations such as short channel effect in MOSFET device as it is unavoidable in scaling. Thus, the aim of this project is to improve the short-channel effect in nanoscale devices. The design parameter standard structure of MetalOxide-Semiconductor Field-Effect Transistor (MOSFET) were proposed referring to the International Technology Roadmap for Semiconductors (ITRS) 2011 edition and compared the structure with same standard structure of ITRS with modification to the junction depth that becomes more shallow source/drain extension (SDE). Silvaco’s DEVEDIT software is used to design the structure of MOSFET with three different gate lengths, while Silvaco’s ATLAS software is used to simulate the structure for data extraction to obtain the output graph. From the output, it shows that, as the size of MOSFET gate length becomes smaller, the threshold voltages also decrease. In improving the SCE, the value of threshold voltage, Vth, is slightly increases on shallower the source/drain extension (SDE). The value of “ON’’ current (ION) also has been extracted for all designs of MOSFET

Optimal Design Of Junctionless Double Gate Vertical MOSFET Using Hybrid Taguchi-GRA With ANN Prediction

Random parameter variations have been an influential factor that deciding the performance of a metal-oxide-semiconductor field effect transistor (MOSFET), especially in nano-scale regime. Thus, controlling the variation of those parameters becomes extremely crucial in order to attain an acceptable performance of an ultra-small MOSFET. This paper proposes an approach to optimally design a n-type junctionless double-gate vertical MOSFET (nJLDGVM) via hybrid Taguchi-grey relational analysis (GRA) with artificial neural networks (ANN) prediction. The device is designed using a combination of 2-D simulation tools (Silvaco) and hybrid Taguchi-GRA with a well-trained ANN prediction. The investigated device parameters consist of channel length (Lch), pillar thickness (Tp), channel doping (Nch) and source/drain doping (Nsd). The optimized design parameters of the device demonstrate a tolerable magnitude of on-state current (ION), off-state current (IOFF), on-off ratio, transconductance (gm), cut-off frequency (fT) and maximum oscillation frequency (fmax), measured at 2344.9 µA/µm, 2.53 pA/µm, 927 x 106, 4.78 mS/µm, 121.5 GHz and 2469 GHz respectively

Effect Of Channel Length Variation On Analog And RF Performance Of Junctionless Double Gate Vertical Mosfet

This paper investigates the effect of channel length (Lch) variation upon analogue and radio frequency (RF) performance of Junctionless Double Gate Vertical MOSFET (JLDGVM). The study has been performed under the fixed level of process parameters by considering the dependence of analogue and RF properties on the channel length. Furthermore, this paper aims to give a comprehensive insight on possible improvement in the performance of analogue and RF of the JLDGVM device. The structure and characteristics of the device are developed and extracted respectively via 2D TCAD simulation. The results show that both transconductance generation factor (TGF) and transconductance (gm) of the JLDGVM device are tremendously increased by 83% and 74% respectively as the scale of channel length is reduced from 12 nm to 9 nm. On the other hand, the unity gain cut-off frequency (fT) and the gain-band-width product (GBW) tremendously improved by ~93% and ~74% respectively as the channel length of the device is scaled from 12 nm to 9 nm

Predictive Analytics Of Cigs Solar Cell Using A Combinational Gra-Mlr-Ga Model

Thin-film Copper Indium Gallium Selenide (CIGS) solar cell is identified to be one of the promising structures to replace conventional silicon-based solar cell due to its lower cost and reduced thickness. Nevertheless, the impact of layer thickness and doping concentration of a window layer - Zinc oxide (ZnO), a buffer layer - Cadmium sulfide (Cds) and an absorber layer (CIGS) needs to be intelligently controlled for more balanced CIGS solar cell performances. Thus, this paper proposes a newly predictive analytics using a combination of Grey relational analysis (GRA), multiple linear regressions (MLR) and genetic algorithm (GA) to optimize the CIGS solar cell parameters for better device performances. The CIGS solar cell model is developed and simulated using solar cell capacitance simulator (SCAPS). The final results prove that the proposed combinational GRA-MLR-GA model has successfully optimized the CIGS solar cell parameters in which ZnO thickness (TZnO), Cds thickness (TCds), CIGS thickness (TCIGS) and CIGS doping concentration (NaCIGS) are predictively optimized to be 0.03 μm, 0.03μm, 2.86 μm and 9.937x1017 cm-3 respectively. The most optimum magnitudes for open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF), and power conversion efficiency (η) after the predictive analytics are measured at 0.8206 V, 32.419 mA/cm2, 83.23% and 22.14% reciprocally

Experimental Performance Analysis Of Macrobending Loss Characteristics In Polymer Optical Fiber

An investigation of bending loss characteristics of a Polymer Optical Fiber is presented experimentally. Loss of optical power in an optical fiber due to bending has been investigated for a wavelength of 650 nm. Variations of bending loss with different lengths have been measured, with a number of radii of curvature. Bending Loss equations for short length POF is proposed, which shows the dependence of bending loss on the curvature radii. The equations can be an initial reference or aid in predicting the loss contributes by the polymer optical fiber